1. Field of the Invention
This invention relates generally to semiconductor devices, and, more particularly, to a semiconductor device structure for well biasing to prevent latch-up or soft errors.
2. Description of Related Art
Complementary metal-oxide semiconductor (CMOS) circuits such as CMOS static random access memory (SRAM) cells encounter problems such as latch-up or soft errors.
In CMOS circuits, latch-up occurs due to the presence of complementary parasitic bipolar transistor structures. Because n-channel and p-channel devices are in close proximity to one other in CMOS circuits, inadvertent (parasitic) p-n-p-n bipolar structures can be found. As a result, under certain biasing conditions, the p-n-p part of the structure can supply base current to the n-p-n structure, causing a large current to flow. This can cause the circuit to malfunction, or even destroy the circuit itself due to heat caused by high power dissipation. The latch-up phenomenon is triggered by a changing current incidental to fluctuation of power supply voltage, a punch through current at a well boundary, or other similar circumstances. Such triggering currents are established in any one or more of a variety of ways, including terminal overvoltage stress, transient displacement currents, ionizing radiation, or impact ionization by hot electrons.
In addition to the problem of latch-up, if energetic particles from the environment, such as alpha-particles, strike a junction, such as the drain junction, surrounded by a depletion region, electrons and holes will be generated within the underlying body of the semiconductor material and will collect along the boundary of the depletion region. The voltage across the junction will thereby be reduced by the charge perturbation. If the charge perturbation is sufficiently large, the stored logic state may be reversed, causing a so called “soft error.” Latch-up and soft errors are both increased by the unstable potential of well stand-by operation at reduced voltage.
A variety of methods for suppressing latch-up and soft error have been proposed. For example, latch-up can be suppressed by providing bias voltages Vss (ground) to the p-well and Vcc (power voltage) to the n-well to set the potentials of the p-well and n-well. One such example is shown in FIG. 1. Referring to FIG. 1, a well-tie implant region 18 is formed having the same conductivity type as a well region 16 to bias the well region 16. The well-tie implant region 18 is separated from the source region 20 in the cell. Unfortunately, this method requires a large area within the cell for forming a separated well-tie implant region 18 and separated contacts 28, 30, substantially decreasing packing density of an integrated circuit. Other similar prior art methods such as one disclosed in U.S. Pat. No. 6,300,661, also require a separate portion of the cell area beside the source region for forming a well-tie region, decreasing the packing density. Also, conventional methods are limited due to precision limits inherent in the photolithography process used in forming these fine structures.
Accordingly, it would be desirable to be able to decrease the amount of space required to bias a well region for preventing latch-up and soft error in CMOS circuits, and thereby reduce cell sizes and increase packing density without being limited by the limitations of photolithography technology.